half adder
英 [hɑːf ˈædə(r)]
美 [hæf ˈædər]
n. 半加器；半加法器
双语例句
- Addend and the summand input, and digital and carry the output device is a half adder.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。 - A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。 - The good performance can be compared with traditional LMS algorithm. As there is only one "1" in the update coefficient, half adder is proposed to get new coefficient, which consumes only 60% hardware and power of traditional LMS algorithm.
提出了用半加器来实现系数自适应调整，量化后的系数更新因子只有一个1，性能可以和传统的LMS算法媲美，硬件规模和功耗只有传统LMS算法的60%。 - The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder ( PFCA) as its carry mode is parallel feedback.
这种新型加法器是一种以半加器为基本结构单元的异步加法器，采用了并行反馈进位方式，称为并行反馈进位加法器（ParallelFeedbackCarryAdder，PFCA）。